John Eldon
Consultant
222 Cereus St
Encinitas, CA 92024
760 942-9406
j.eldon@sbcglobal.net
SPECIALIZATION
VLSI DSP SystemVerilog RTL design and verification
science and technology education
SERVICES
translation of mathematical algorithms into silicon architectures
RTL design and verification of VLSI circuits (FPGA or custom ASIC) using SystemVerilog or VHDL
real-time digital signal processing, including filters and spectral analysis
mathematics, physical science, and technology education
EXPERIENCE
3 patents granted
plus 2 pending in communications and video
semiconductor design
(28 years) including some applications engineering and some management and project lead responsibilities
patent committee
(5 years) intellectual property and infringement issues
teaching
(16 years) UCSD Extension -- created introductory and advanced courses on digital design with SystemVerilog and VHDL
statistical analysis
(4 years) air pollution databases, plus associated program management responsibilities
EDUCATION
BS Physics, UCLA
MS Physics, UCLA
solid state and physics education
DEnv, UCLA
Doctor of Environmental Science & Engineering -- mathematical model of photochemical smog formation
PUBLICATIONS
Most recent: 2007 Verigy User Group conference: "At-Speed Testing of a UWB Transceiver." Problem addressed: automated testing of a mixed-signal digital/analog communications RF transceiver circuit with a 16-bit-wide 675Ms/s bus
ASSOCIATIONS
Senior Member, IEEE
member, San Diego Science Alliance